Video resolution is defined by number of pixels per frame. For example, a video signal of resolution of 480 p has 720 active pixels per line and 480 active lines per frame, and a video signal of resolution of 1080 p has 1920 active pixels per line and 1080 active lines per frame. The display frequency or frame rate is defined by the number of frames displayed per second, and the standard display frequencies include 23.9 Hz, 24 Hz, 50 Hz, 59.94 Hz and 60 Hz. Video signals are normally generated by diverse video sources (e.g., video cameras, web cams, digital camcorders, digitized optical pictures) and different video sources typically generate video signals with different resolutions and display frequencies.
Modern display devices display video one pixel at a time based on a clock cycle. Displaying output video on a screen is analogous to continuously drawing a box from left to right and from top to bottom. The clock signal provides a timing reference for each pixel. Horizontal and vertical synchronization signals are used to indicate the start of each new line and frame respectively. In this analogy, the horizontal sync signal indicates when to jump from right to left (to start the new line) and the vertical sync signal indicates when to jump from the bottom of the box to the top (to start the new frame). For example, FIG. 1 shows the clock signal CLK relative to the horizontal sync signals HSYNC for a video signal of 480 p resolution, and FIG. 2 shows the horizontal sync signals HSYNC relative to the vertical signals VSYNC for the video signal of 480 p resolution. As shown in FIG. 1, each line has 858 total horizontal clocks during a data enable cycle, of which 720 are active horizontal clocks when the data enable signal is active. Further, as shown in FIG. 2, each frame has 525 lines, of which 45 are blanking lines with the data enable signal being non-active and 480 lines are active with the data enable signal turning on periodically.
With the wide availability of the high-definition display devices, a lot of video signals with different resolutions need to be scaled to take advantage of the capability of the display devices (e.g., from 480 p to 720 p or even 1080 p). Further, the display frequencies can also be increased (e.g., from 24 Hz to 60 Hz or even 120 Hz to display smoother motion on moving scenes). A video scaler converts video data from one resolution to another and changes the display frequencies if needed. Both input and output resolutions can be any video or graphics standard. In a typical application, the output video resolution is fixed (determined by the native resolution of the display device) and the input video timing/resolution will change as inputs change. For example, the input is changed from 480 p to 720 p but the output is still fixed at 1080 p.
The video scalers typically transfer video signals one pixel at a time. That is, the scalers input or output one pixel for one clock cycle. Both input and output timing for the scalers also consists of clock, horizontal synchronization (sync), and vertical sync signals, and sometimes other synchronization signals. Because the input and output signal resolutions are different, the input and output are running at different clock speeds (e.g., 480 p at 27 MHz clock, 1080 p at 148.5 MHz clock). However, as the input source or resolution changes it is desirable for the output timing to remain unchanged because a stable output timing base makes it possible for down stream devices to retain lock during input changes and insures that there is minimal disruption to the displayed picture.
In some implementations, the timing signals are generated using simple counters which wrap around when reaching the desired number of samples per line (horizontal sync) and lines per frame (vertical sync). The timing system is complicated by the fact that almost all video standards can operate at two different clock frequencies to accommodate slightly different frame rates of 60 Hz and 59.94 Hz. So, for example, a video signal with 480 active lines per frame and 720 active pixels per line can have a clock frequency of 27 MHz (59.94 Hz) or 27.027 MHz (60 Hz). In either frequency, there is a fixed number of clocks between each horizontal synchronization pulse and also a fixed number of horizontal synchronization pulses between each vertical synchronization pulse per video standard.
The present scaler technology has several problems. For example, the input video (resolution or source) can be changed, but the output resolution is to be kept constant. If the output video timing is directly phase and frequency locked to the input timing, the discontinuity caused by changing the input will be passed directly to the output. This discontinuity will adversely affect downstream video sinks (i.e. display devices) resulting in the final display being disrupted or blanked for a period of time. However, if the scaler output timing is free running and not locked to the input, the disruption of output timing is eliminated but this will lead to frames of video data being either dropped or repeated to compensate for the frequency differences between input and output timing. Video frame drops and repeats cause unsightly artifacts on the final displayed picture such a stuttering motion. Further to these problems, the accuracy of the source generated clock will also vary slightly from source to source such that an exact 27 MHz or 27.027 MHz is extremely unlikely. Therefore, there is a need in the art for providing a video signal processor that can seamless fast switch between different input sources.